The latest PCIe 6.x specification brings groundbreaking advancements in power efficiency and performance optimization. In this technical demonstration, ...

SoC designers face rapid expansion in architecture, time-to-market pressures, scarcity of expertise, suboptimal utilization ...

Andes Technology today announced that its D45-SE processor has successfully achieved ISO 26262 ASIL-D with the certification of SGS TÜV. This certification marks a significant achievement for Andes ...

Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early days. Involved ...

Latest Virtuoso Studio release and Spectre Simulator deliver a 30% productivity gain for MediaTek’s 2nm design flow compared ...

Partnering with industry giants such as Arm and Keysight, Alphawave Semi will highlight its leadership in UCIe, HBM, and next ...

VeriSilicon (688521.SH) today announced the joint launch of the second-generation Yunbao series 5G RedCap/4G LTE dual-mode ...

Under this agreement, Ambarella will utilize Qualitas C/D-PHY IP, implemented on the 5nm process, to apply it to its ...

Hezi Saar of Synopsys appointed board chair; new vice chair and treasurer named for global organization developing interface ...

Using Samsung Foundry's SF4X 4nm advanced process, the latest BlueLynx PHY supports both standard 2D and advanced 2.5D ...

As we enter 2025, I am pleased to announce PCIe 7.0 specification, version 0.7 is now available for member review. This ...

As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. System and chip designers ...